The Defense Advanced Research Projects Agency (DARPA) is supporting new research to provide on-chip liquid cooling in field-programmable gate array (FPGA) devices – but successful demonstrations to date indicate that the technology could be easily adapted for conventional CPUs and GPUs, and additionally that it has the potential to reduce the size of devices, allow for chip stacking, dispense with heat sinks and fans and significantly extend the life-span of chips.

At the IEEE Custom Integrated Circuits Conference, 2015 Thomas E. Sarvey, Graduate Research Assistant at the Georgia Institute of Technology, presented the paper Embedded Cooling Technologies for Densely Integrated Electronic Systems, which outlines his research group’s progress to date.

“We have eliminated the heat sink atop the silicon die by moving liquid cooling just a few hundred microns away from the transistors,” said Muhannad Bakir, associate professor and ON Semiconductor Junior Professor in the Georgia Tech School of Electrical and Computer Engineering. “We believe that reliably integrating microfluidic cooling directly on the silicon will be a disruptive technology for a new generation of electronics.”

The technique involves cutting microfluidic channels into the die of FPGA devices, which were chosen for the research and trials because of their flexible configuration and extensive use in the military. Effectively this locates the cooling just microns from the problem, and even allows for the possibility of chip-stacking, which very few devices currently have the room or efficiency to achieve, given the necessity to dissipate heat from a central locus of adjacent chips.

The group successfully developed a standard demonstration test, including one for DARPA officials, in which a converted FPGA with bespoke Altera-supplied architecture operated, with no other cooling, at less than 24 degrees Celsius, and was compared to an analogous air-cooled device operating at 60 degrees Celsius.

The system was described as a ‘real electronic platform’ by Georgia Tech School of Electrical and Computer Engineering professor Sudhakar Yalamanchili.

On-chip liquid cooling also opens up the possibility for a new level of compactness in device design, which frequently has to leverage available surface space for dissipation purposes, often to the alarm of the end user.

In a separate project Prof. Bakir is investigating the potential of copper vias mounted through silicon columns within the cooling structure of the FPGA setups. Bakir said: “By bringing system components closer together, we can reduce interconnect length and that will lead to improvements in bandwidth density and reductions in energy use.”